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IS82C37A-12

Part Number	IS82C37A-12
Manufacturer	Harris Corporation
Description	CMOS High Performance Programmable DMA Controller
Published	Apr 7, 2005
Detailed Description	S E M I C O N D U C T O R 82C37A CMOS High Performance Programmable DMA Controller Description The 82C37A is an enhance...
Datasheet	IS82C37A-12 PDF File

Overview

S E M I C O N D U C T O R 82C37A CMOS High Performance Programmable DMA Controller Description The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Harris’ advanced 2 micron CMOS process.
Pin compatible with NMOS designs, the 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption.
The fully static design permits gated clock operation for even further reduction of power.
The 82C37A controller can improve system performance by allowing external devices to transfer data directly to or from system memory.
Memory-to-memory transfer capability is also provided, along with a memory block initialization feature.
DMA requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for ﬂexible operation.
The 82C37A is designed to be used with an external address latch, such as the 82C82, to demultiplex the most signiﬁcant 8-bits of address.
The 82C37A can be used with industry standard microprocessors such as 80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and others.
Multimode programmability allows the user to select from three basic types of DMA services, and reconﬁguration under program control is possible even with the clock to the controller stopped.
Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process).
March 1997 Features • Compatible with the NMOS 8237A • Four Independent Maskable Channels with Autoinitialization Capability • Cascadable to any Number of Channels • High Speed Data Transfers: - Up to 4MBytes/sec with 8MHz Clock - Up to 6.
25MBytes/sec with 12.
5MHz Clock • Memory-to-Memory Transfers • Static CMOS Design Permits Low Power Operation - ICCSB = 10µA Maximum - ICCOP = 2mA/MHz Maximum • Fully TTL/CMOS Compatible • Internal Registers may be Read from Software...

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