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K4S560832D

Samsung semiconductor
Part Number K4S560832D
Manufacturer Samsung semiconductor
Description 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL
Published Apr 7, 2005
Detailed Description K4S560832D CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 May. 2003 * Samsung Elec...
Datasheet PDF File K4S560832D PDF File

K4S560832D
K4S560832D


Overview
K4S560832D CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 1.
1 May.
2003 * Samsung Electronics reserves the right to change products or specification without notice.
Rev.
1.
1 May.
2003 K4S560832D Revision History Revision 0.
0 (Jan.
, 2002) - First release CMOS SDRAM Revision 0.
1(May.
, 2003) - ICC6 of Low power is changed from 1.
0 to 1.
5 due to typo.
Rev.
1.
1 May.
2003 K4S560832D 8M x 8Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (8K Cycle) Part No.
K4S560832D-TC/L7C K4S560832D-TC/L75 K4S560832D-TC/L1H K4S560832D-TC/L1L CMOS SDRAM GENERAL DESCRIPTION The K4S560832D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION Max Freq.
133MHz(CL=2) 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54pin TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control LWE LDQM Data Input Register Bank Select 8M x 8 Sense AMP 8M x 8 8M x 8 8M x 8 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register CLK ADD Column Decoder Col.
Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Timing Register Programming Register LWCBR LDQM CLK CKE CS R...



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