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K4S641632D

Samsung semiconductor
Part Number K4S641632D
Manufacturer Samsung semiconductor
Description 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Published Apr 7, 2005
Detailed Description K4S641632D CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.3 June 2000 * Samsung Elec...
Datasheet PDF File K4S641632D PDF File

K4S641632D
K4S641632D


Overview
K4S641632D CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.
3 June 2000 * Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
3 June 2000 K4S641632D Revision History Revision 0.
1 (May 2000) • Changed tOH of K4S280432C-TC75/TL75 from 2.
7ns to 3.
0ns.
CMOS SDRAM Revision 0.
2 (May 2000) • Added -70 (7.
0ns) Speed.
Revision 0.
3 (June 2000) • Added -60 (6.
0ns) and -55(5.
5ns) Speed.
Rev.
0.
3 June 2000 K4S641632D 1M x 16Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.
3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S641632D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
• • • • • ORDERING INFORMATION Part No.
K4S641632D-TC/L55 K4S641632D-TC/L60 K4S641632D-TC/L70 K4S641632D-TC/L75 K4S641632D-TC/L80 K4S641632D-TC/L1H K4S641632D-TC/L1L Max Freq.
183MHz(CL=3) 166MHz(CL=3) 143MHz(CL=3) 133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54 TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 1M x 16 Sense AMP 1M x 16 1M x 16 1M x 16 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address ...



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