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K9F5608U0A

Samsung semiconductor
Part Number K9F5608U0A
Manufacturer Samsung semiconductor
Description 32M x 8 Bit NAND Flash Memory
Published Apr 7, 2005
Detailed Description K9F5608U0A-YCB0,K9F5608U0A-YIB0 Document Title 32M x 8 Bit NAND Flash Memory FLASH MEMORY Revision History Revision No...
Datasheet PDF File K9F5608U0A PDF File

K9F5608U0A
K9F5608U0A

Overview
K9F5608U0A-YCB0,K9F5608U0A-YIB0 Document Title 32M x 8 Bit NAND Flash Memory FLASH MEMORY Revision History Revision No.
History 0.
0 Initial issue.
Draft Date July 17th 2000 Remark Advanced Information Preliminary 0.
1 1.
Support copy-back program - The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within the same array without utilizing an external memory.
Since the time-con suming sequently-reading and its re-loading cycles are removed, the system performance is improved.
The benefit is especially obvious when a portion of a block is updated so that the rest of the block also need to be copied to the newly assigned free block.
Oct.
4th 2000 0.
2 Nov.
20th 2000 1.
Explain how pointer operation works in detail.
2.
For partial page programming into the copied page - Once the copy-back Program is finished, any additional partial page programming into the copied pages is prohibited before erase.
3.
Renamed GND input (pin # 6) on behalf of SE (pin # 6) - The SE input controls the access of the spare area.
When SE is high, the spare area is not accessible for reading or programming.
SE is rec ommended to be coupled to GND or Vcc and should not be toggled during reading or programming.
=> Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.
4.
Updated operation for tRST timing - If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
1.
In addition, explain WE function in pin description - The WE must be held high when outputs are activated.
1.
Powerup sequence is added : Recovery time of minimum 1µs is required before internal circuit gets ready for any command sequences ~ 2.
5V Preliminary 0.
3 Mar.
2th 2001 0.
4 Jul.
22th 2001 ≈ ~ 2.
5V VCC High WP WE 2.
AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3.
AC parameter tAR1 value : 100ns --> 20ns Note : For more detailed fea...


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