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SM8213AM

Part Number	SM8213AM
Manufacturer	Nippon Precision Circuits Inc
Description	POCSAG Decoder For Multiframe Pagers
Published	Apr 7, 2005
Detailed Description	SM8213AM NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Multiframe Pagers OVERVIEW The SM8213AM is a POCSAG-standar...
Datasheet	SM8213AM PDF File

Overview

SM8213AM NIPPON PRECISION CIRCUITS INC.
POCSAG Decoder For Multiframe Pagers OVERVIEW The SM8213AM is a POCSAG-standard (Post Ofﬁce Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes.
The SM8213AM supports call messages in either tone, numerical or character outputs at signal speeds of 512, 1200 or 2400 bps.
The signal input stage features a built-in ﬁlter.
Each of the addresses (max.
7 + 1 dummy = 8) can be assigned to any frame, which also makes the device conﬁgurable for many additional services.
Each address can be independently set to ON/OFF.
Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU time required.
Intermittent-duty method (battery saving (BS) method) control signals, compatible with PLL operation, and Molybdenum-gate CMOS structure makes possible the construction of low-voltage operation, low power dissipation systems.
The SM8213AM is available in 16-pin SSOPs.
s s s s s s s s 25 to 75% duty factor signal coverage 8 rate error detection condition settings 76.
8 kHz system clock (crystal oscillator) 76.
8 or 38.
4 kHz clock output pin Built-in oscillator capacitor and feedback resistor 2.
0 to 3.
5 V operating supply voltage Molybdenum-gate CMOS process realizes low power dissipation 16-pin SSOP PINOUT Top View BS1 BS2 BS3 SIGNAL XVSS XT XTN VSS 1 16 VDD ATTN SDI SDO SCK AREA RSTN CLKO 8213AM 8 9 FEATURES s s s PACKAGE DIMENSIONS Unit: mm s s s s 0.
05 0.
05 1.
5 0.
1 s s s s s Conforms to POCSAG standard for pagers 512, 1200 or 2400 bps signal speed Multiframe compatible (each address individually controllable) 8 addresses × 4 sub-addresses (total of 32 addresses) control (8 addresses comprise 7 actual addresses + 1 dummy address) Built-in buffer memory (1 code word) Supports tone, numeric or character call messages Built-in inpu...

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SM8213AM POCSAG Decoder For Multiframe Pagers - Nippon Precision Circuits Inc

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