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ICS83115BRT

Integrated Circuit Systems
Part Number ICS83115BRT
Manufacturer Integrated Circuit Systems
Description LOW SKEW/ 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Published Apr 16, 2005
Detailed Description Integrated Circuit Systems, Inc. ICS83115 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER FEATURES • 16 LVCMOS/LVTTL out...
Datasheet PDF File ICS83115BRT PDF File

ICS83115BRT
ICS83115BRT

Overview
Integrated Circuit Systems, Inc.
ICS83115 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER FEATURES • 16 LVCMOS/LVTTL outputs • 1 LVCMOS/LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • Part-to-part skew: 800ps (maximum) • Additive phase jitter, RMS: 0.
09ps (typical) • 3.
3V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free package available • Industrial temperature information available upon request GENERAL DESCRIPTION The ICS83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS.
The ICS83115 single ended clock input accepts LVCMOS or LVTTL input levels.
The ICS83115 operates at full 3.
3V supply mode over the commercial temperature range.
Guaranteed output and part-topart skew characteristics make the ICS83115 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS BLOCK DIAGRAM OE2 VDD PIN ASSIGNMENT 4 OE1 Q0 Q1 Q2 VDD VDD Q3 Q4 GND GND Q5 Q6 Q7 IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OE2 Q15 Q14 Q13 VDD VDD Q12 Q11 GND GND Q10 Q9 Q8 OE0 IN Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 OE2 OE1 ICS83115 28-Lead SSOP, 150mil 9.
9mm x 3.
9mm x 1.
7mm body package R Package (Top View) 4 OE1 GND OE0 83115BR www.
icst.
com/products/hiperclocks.
html 1 REV.
A SEPTEMBER 21, 2004 OE0 OE2 Integrated Circuit Systems, Inc.
ICS83115 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER Type Input Pullup Description Output enable.
When LOW, forces outputs Q2 thru Q7 to HiZ state.
5V tolerant.
LVCMOS/LVTTL interface levels.
TABLE 1.
PIN DESCRIPTIONS Number 1 2, 3, 4, 7, 8, 11, 12, 13, 16, 17, 18, 21, 22, 25, 26, 27 5, 6, 23, 24 9, 10, 19, 20 14 Name OE1 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 VDD GND IN Output LVCMOS/LVTTL clock outputs.
7Ω typical output impedanc...


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