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XC2V1000-4FG456I

Xilinx
Part Number XC2V1000-4FG456I
Manufacturer Xilinx
Description Field-Programmable Gate Arrays
Published Apr 16, 2005
Detailed Description 0 R Virtex-II 1.5V Field-Programmable Gate Arrays 0 0 DS031-1 (v1.7) October 2, 2001 Advance Product Specification ...
Datasheet PDF File XC2V1000-4FG456I PDF File

XC2V1000-4FG456I
XC2V1000-4FG456I

Overview
0 R Virtex-II 1.
5V Field-Programmable Gate Arrays 0 0 DS031-1 (v1.
7) October 2, 2001 Advance Product Specification Summary of Virtex®-II Features • • Industry First Platform FPGA Solution IP-Immersion™ Architecture - Densities from 40K to 8M system gates - 420 MHz internal clock speed (Advance Data) - 840+ Mb/s I/O (Advance Data) SelectRAM™ Memory Hierarchy - 3 Mb of True Dual-Port™ RAM in 18-Kbit block SelectRAM resources - Up to 1.
5 Mb of distributed SelectRAM resources - High-performance interfaces to external memory · DDR-SDRAM interface · FCRAM interface · QDR™-SRAM interface · Sigma RAM interface Arithmetic Functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible Logic Resources - Up to 93,184 internal registers / latches with Clock Enable - Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products support - Internal 3-state bussing High-Performance Clock Management Circuitry - Up to 12 DCM (Digital Clock Manager) modules · Precise clock de-skew · Flexible frequency synthesis · High-resolution phase shifting - 16 global clock multiplexer buffers Active Interconnect™ Technology - Fourth generation segmented routing structure - Predictable, fast routing delay, independent of fanout SelectI/O-Ultra™ Technology - Up to 1,108 user I/Os - 19 single-ended standards and six differential standards - Programmable sink current (2 mA to 24 mA) per I/O Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards - PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz compliance, and CardBus compliant - Differential Signaling · 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers · Bus LVDS I/O · Lightning Data Transport (LDT) I/O with current driver buffers · Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O · Built-in DDR Input and Output registers -...


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