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XCR3064XL-7CS48I

Xilinx
Part Number XCR3064XL-7CS48I
Manufacturer Xilinx
Description XCR3064XL 64 Macrocell CPLD
Published Apr 16, 2005
Detailed Description 0 R XCR3064XL 64 Macrocell CPLD 0 14 DS017 (v1.6) January 8, 2002 Product Specification Features • • • • • Lowest p...
Datasheet PDF File XCR3064XL-7CS48I PDF File

XCR3064XL-7CS48I
XCR3064XL-7CS48I

Overview
0 R XCR3064XL 64 Macrocell CPLD 0 14 DS017 (v1.
6) January 8, 2002 Product Specification Features • • • • • Lowest power 64 macrocell CPLD 6.
0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages • • 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.
3V core supply Advanced 0.
35 micron five layer metal EEPROM process Fast Zero Power™ (FZP) CMOS design technology In-system programming Predictable timing model Up to 23 available clocks per function block Excellent pin retention during design changes Full IEEE Standard 1149.
1 boundary-scan (JTAG) Four global clocks Eight product term control terms per function block Description The XCR3064XL is a 3.
3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.
A total of four function blocks provide 1,500 usable gates.
Pin-to-pin propagation delays are 6.
0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast Zero Power Xilinx offers a TotalCMOS CPLD, both in process technology and design technique.
Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach.
This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance.
Refer to Figure 1 and Table 1 showing the ICC vs.
Frequency of our XCR3064XL TotalCMOS CPLD (data taken with four resetable up/down, 16-bit counters at 3.
3V, 25 °C).
35.
0 30.
0 Optimized for 3.
3V systems Advanced system features Input registers Typical ICC (mA) 25.
0 20.
0 15.
0 10.
0 5.
0 0.
0 0 20 40 60 80 100 120 140 • • • • • • Fast ISP programming times Port Enable pin for dual function of JTAG IS...


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