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X25640

Xicor
Part Number X25640
Manufacturer Xicor
Description Advanced SPI Serial E2PROM With Block LockTM Protection
Published Apr 16, 2005
Detailed Description APPLICATION NOTES A V A I L A B L E X25640 64K AN19 • AN38 • AN41 • AN61 X25640 DESCRIPTION 8K x 8 Bit Advanced SPI...
Datasheet PDF File X25640 PDF File

X25640
X25640

Overview
APPLICATION NOTES A V A I L A B L E X25640 64K AN19 • AN38 • AN41 • AN61 X25640 DESCRIPTION 8K x 8 Bit Advanced SPI Serial E2PROM With Block LockTM Protection FEATURES • • • • • • • • • • • 1MHz Clock Rate Low Power CMOS —200µA Standby Current —5mA Active Current 5 Volt Power Supply SPI Modes (0,0 & 1,1) 8K X 8 Bits —32 Byte Page Mode Block Lock Protection —Protect 1/4, 1/2 or all of E2PROM Array Built-in Inadvertent Write Protection —Power-Up/Power-Down protection circuitry —Write Enable Latch —Write Protect Pin Self-Timed Write Cycle —5ms Write Cycle Time (Typical) High Reliability —Endurance: 100,000 cycles —Data Retention: 100 Years —ESD protection: 2000V on all pins 8-Lead PDlP Package 14-Lead SOIC Package The X25640 is a CMOS 65,536-bit serial E2PROM, internally organized as 8K x 8.
The X25640 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus.
The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus.
The X25640 also features two additional inputs that provide the end user with added flexibility.
By asserting the HOLD input, the X25640 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts.
The WP input can be used as a hardwire input to the X25640 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25640 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM STATUS REGISTER WRITE PROTECT LOGIC X DECODE LOGIC 64 64 X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 64 64 X 256 8K BYTE ARRAY 128 128 X 256 WP WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE DATA REGISTER 3089...


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