DatasheetsPDF.com

UPF01002

Infineon Technologies
Part Number UPF01002
Manufacturer Infineon Technologies
Description 10 Gigabit/s Ethernet Transceiver
Published Apr 16, 2005
Detailed Description PRODUCT BRIEF 10 Gigabit/s Ethernet Transceiver with OC-192c Framer and XAUI Interface The TenGiPHY-W is a single chip ...
Datasheet PDF File UPF01002 PDF File

UPF01002
UPF01002

Overview
PRODUCT BRIEF 10 Gigabit/s Ethernet Transceiver with OC-192c Framer and XAUI Interface The TenGiPHY-W is a single chip transceiver IC for 10 Gbit/s Ethernet and Fibre Channel connectivity.
It offers a serial, full duplex 10 Gbit/s interface to an optical sub-module.
The integrated CDR and CMU operate at data rates between 9.
95328 and 10.
51875Gbit/s.
The TenGiPHY-W provides the XGXS, PCS and PMA sublayers of the 10G Ethernet and Fibre Channel standards.
For WAN applications a standard OC-192/STM-64 SONET/SDH framer together with flexible clocking modes enables a direct connection to the public network without additional components.
The networking system can control the chip via a narrow-width MDIO interface by writing and reading its control and status registers.
Applications ■ ■ ■ ■ ■ Fiber optic modules according to the XENPAK multi-source agreement 10 Gbit/s Ethernet and Fibre Channel line cards Ethernet backbones in Metro Area Networks Terabit Routers ■ ■ Features ■ ■ ■ ■ ■ ■ ■ Complete 10 Gbit/s Ethernet and Fibre Channel PHY supporting WAN and LAN applications Complies with IEEE 802.
3ae Compliant to XENPAK multisource agreement Complies with ANSI 1413-D Embedded µController allows for control and tuning of the PMDs via analog interfaces Clock & data recovery and clock multiplying unit without external loop filter components ■ ■ ■ Complies with jitter tolerance and jitter transmit requirements according to Telcordia GR-1244CORE and ITU-T G.
825 Supports various clocking modes based on external reference clocks, loop- and external timing Integrated bit error rate tester (BERT) usable for multiple atspeed diagnostic scenarios Includes the XGXS, PCS, WIS, and PMA sublayers of the OSI protocol stack Synchronization and de-skewing of XAUI lanes Integrated standard STS-192/ STM-64 SONET/SDH framer according to GR-253-CORE, ANSI T1.
105/416, ITU-T G.
707.
Optionally maps/extracts 10 Gbit/s Ethernet packets into/ from the STS-192c/VC4-64c payload or con...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)