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U2102B

TEMIC Semiconductors
Part Number U2102B
Manufacturer TEMIC Semiconductors
Description Multifunction Timer
Published Apr 16, 2005
Detailed Description U2102B Multifunction Timer Description The monolithic integrated bipolar circuit U2102B is an MOSFET or IGBT control cir...
Datasheet PDF File U2102B PDF File

U2102B
U2102B

Overview
U2102B Multifunction Timer Description The monolithic integrated bipolar circuit U2102B is an MOSFET or IGBT control circuit which allows realization of an extremely wide range of timer and dimmer functions.
The integrated current monitoring function additionally permits the power switch to be reliably protected without an additional fuse.
Features D Integrated reverse phase control D Two- or three-wire applications D Mode selection: – Zero-voltage switch with static output – Two-stage reverse phase control with switch-off – Two-stage reverse phase control D Adjustable and retriggerable tracking time D External window adjustment for sensor input D Enable input for triggering Applications D D D D D Motion detectors Time-delay relays Dimmers Reverse phase controls Timers D Current monitoring: – High-speed short-circuit monitoring with output – High-current monitoring with integrating buffer D Integrated chip temperature monitoring Package: DIP16, SO16 94 8666 1 VRef 2 3 4 Voltage monitoring 16 Synchronization 15 Voltage limitation Control 13 Reverse phase control 5 RC oscillator Divider logic Push pull 14 12 6 Programing Current monitoring 11 Triggering with buffers 7 8 9 Temperature monitoring Test logic 10 Figure 1.
Block diagram TELEFUNKEN Semiconductors Rev.
A1, 30-May-96 1 (16) U2102B 68 k W +Vs 15 47 mF/25 V C1 14 IGBT RG Load 1 kW 2 Push pull Ramp Voltage limitation R2 Reverse Phase + 4 – 12 Control GND 13 100 W Temp monitoring 1 MW 10 nF C3 22 k W 820 k W 3 R3 Rsh 100kW 5 RC oscillator Divider Control VRef Stat.
ZVS logic 6 + VS 2 stage / out GND 0.
02xVRef Control CRef Voltage monitoring Current monitoring + – Buffer 120 ms Clock Test logic Clock POR – + 1 mF C2 220 nF Q Q R S 1 kW 500 mV 11 1 nF 100 mV VRef + VS 2 stage GND Figure 2.
Block diagram with typical circuit for dc loads Enable 0.
1/0.
4/ 0.
5 x VRef 0.
55 x VRef + 0.
2 V 9 7 Enable Test mode Buffer (spikefilter) 10 V Ref + 8 – Trigger window + – 0.
45 x VR...


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