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TQ8016

TriQuint Semiconductor
Part Number TQ8016
Manufacturer TriQuint Semiconductor
Description 1.3 Gigabit/sec 16x16 Digital ECL Crosspoint Switch
Published Apr 16, 2005
Detailed Description T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8016 D0..15 D0..15 Input Buffers 16 x 16 Crosspoint Switch...
Datasheet PDF File TQ8016 PDF File

TQ8016
TQ8016

Overview
T R I Q U I N T S E M I C O N D U C T O R, I N C .
TQ8016 D0.
.
15 D0.
.
15 Input Buffers 16 x 16 Crosspoint Switch Matrix 64 CONFIGURE (R2) Sixteen 4-Bit Latches 64 (R1) Sixteen 4-Bit Addressable Output Select Latches 4:16 Decoder VCC VEE OA0.
.
3 4 TQ8016 GND Output Buffers O0.
.
15 O0.
.
15 1.
3 Gigabit/sec 16x16 Digital ECL Crosspoint Switch SWITCHING PRODUCTS RESET LOAD IA0.
.
3 4 The TQ8016 is a 16 x 16 differential digital crosspoint switch capable of handling 1.
3 Gbit/s data rate.
The high data rate and exceptional signal fidelity is made possible with TriQuint's fully differential Source-Coupled FET Logic (SCFL) standard cells.
The symmetrical switching characteristic inherent in differential logic results in low signal skew and crosstalk for maximum signal fidelity.
The user can independently configure any switch output to any input, including an input chosen by another output.
To configure the switch, the 4-bit output address (OA0.
.
3) is decoded to enable the loading of the 4-bit input selection data (IA0.
.
3) on the rising edge of the LOAD signal.
The process is repeated until all desired connections are programmed.
By bringing the CONFIGURE signal high, the contents of the Output Select Latches are transferred in parallel to a second row of 4-bit latches (R2), causing the switch reconfiguration.
This double row architecture minimizes the time to completely reconfigure the switch since a new set of addresses can be loaded to the Output Select Latches (R1) while the switch is active (transmitting).
At the time of reconfiguration, no data drop-out occurs for any output whose input connection does not change.
For applications which do not require synchronous configuration of the switch, the LOAD and CONFIGURE inputs may be tied together.
Typical output waveform with all channels driven Features • >1.
3 Gigabit/sec data rate • Non-blocking architecture • +200 ps delay match (one input to all outputs) • ECL-level data inputs/outputs; CMOS-level control inputs ...


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