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TP11362

National Semiconductor
Part Number TP11362
Manufacturer National Semiconductor
Description Quad Adaptive Differential PCM Processor
Published Apr 16, 2005
Detailed Description TP11362A Quad Adaptive Differential PCM Processor March 1997 TP11362A Quad Adaptive Differential PCM Processor General...
Datasheet PDF File TP11362 PDF File

TP11362
TP11362

Overview
TP11362A Quad Adaptive Differential PCM Processor March 1997 TP11362A Quad Adaptive Differential PCM Processor General Description The TP11362A is a quad (4) channel Adaptive Differential Pulse Code Modulation (ADPCM) transcoder, fully compatible to ITU G.
726 recommendation in 40 kbps, 32 kbps, 24 kbps, 16 kbps and ANSI 32 kbps modes.
The TP11362A ADPCM processor can operate on up to 8 independent channels in an 8 kHz frame.
Each channel is individually configured, supporting both full and half duplex operation.
All input/output transfers occur on an interrupt basis using serial, double buffered data registers.
Together with National’s TP3054/57 COMBO ® or TP3070/71 COMBO II devices, the TP11362A forms complete ADPCM channels with Codec/ filtering.
Features n CCITT G.
726 compatible at 40, 32, 24, 16 kbps n ANSI T1.
301 compatible at 32 kbps n 8-channel half-duplex (encode or decode) or 4-channel full-duplex operation in 8 kHz frame n Each channel individually configurable n Selectable µ-law or A-law PCM coding n Asynchronous 8 MHz master clock operation n TTL and CMOS compatible inputs and outputs n 28-pin PLCC or 24-pin DIP packages n Power consumption of typ.
6 mW at +5V per full-duplex channel n On-Chip Power-On-Reset n −40˚C to +85˚C operating temperature range n Single 5V supply Block Diagram DS012877-1 FIGURE 1.
Block Diagram TRI-STATE ® and COMBO ® are registered trademarks of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation DS012877 www.
national.
com Connection Diagrams Plastic Chip Carriers Plastic Dual-In-Line DS012877-2 DS012877-3 Top View Order Number TP11362AV See NS Package Number V28A Top View Order Number TP11362AN See NS Package Number N24A CLK Master clock input.
CLK may be asynchronous to PSCK or ASCK.
CE Chip enable input.
When CE is high, it enables data transfer.
The falling edge of CE latches and transfers the serial data TSI or RSI to the core for processing and strobes the control signals QSEL0, QSEL...


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