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IDT7M1024

Part Number	IDT7M1024
Manufacturer	Integrated Device
Description	4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
Published	Apr 17, 2005
Detailed Description	4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE Integrated Device Technology, Inc. IDT7M1024 FEATURES: • High-d...
Datasheet	IDT7M1024 PDF File

Overview

4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE Integrated Device Technology, Inc.
IDT7M1024 FEATURES: • High-density 4K x 36 Synchronous Dual-Port SRAM module • Architecture based on Dual-Port RAM cells — Allows full simultaneous access from both ports • Synchronous operation — 4ns set-up to clock, 1ns hold on all control, data, and address inputs — Data input, address, and control registers — Fast 20ns clock to data out — Self-timed write allows fast write cycle • Clock enable feature • Single 5V (±10%) power supply • Multiple GND pins and decoupling capacitors for maximum noise immunity • Inputs/outputs directly TTL-compatible DESCRIPTION: The IDT7M1024 is a 4K x 36 bit high-speed synchronous Dual-Port Static RAM module constructed on a co-fired ce- ramic substrate using four IDT7099 (4K x 9) Dual-Port RAMs.
The IDT7M1024 module is designed to be used as a standalone 36-bit Dual-Port Static RAM.
The IDT7M1024 provides a true synchronous Dual-Port Static RAM interface.
Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs.
All internal registers are clocked on the rising edge of the clock signal.
An asynchronous output enable is provided to ease asynchronous bus interfacing.
The internal write pulse width is independent of the HIGH and LOW periods of the clock.
This allows the shortest possible realized cycle times.
Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications.
The data inputs are gated to control on-chip noise in bussed applications.
The user must guarantee that the R/W pins are LOW for at least one clock cycle before any write is attempted.
A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption.
The IDT7M1024 module is packaged in a 142-lead ceramic FUNCTIONAL BLOCK DIAGRAM L_CLK L_CLKENL L_CEL L_OEL L_A0 – 11...

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