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UPD703014AY

NEC
Part Number UPD703014AY
Manufacturer NEC
Description 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
Published Apr 17, 2005
Detailed Description DATA SHEET µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY V850/SA1 32-/16-BIT SINGLE-CHIP MICROCONTROLLER T...
Datasheet PDF File UPD703014AY PDF File

UPD703014AY
UPD703014AY


Overview
DATA SHEET µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY V850/SA1 32-/16-BIT SINGLE-CHIP MICROCONTROLLER TM MOS INTEGRATED CIRCUIT DESCRIPTION The µPD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit singlechip microcontrollers that include the CPU core of the V850 FamilyTM, and peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.
In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1 includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions, all of which are instructions suited to digital servo control applications.
As a real-time control system, this device provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).
Detailed function descriptions are provided in the following user’s manuals.
Be sure to read them before designing.
V850/SA1 User’s Manual Hardware: U12768E TM U10243E V850 Family User’s Manual Architecture: FEATURES { Number of instructions: 74 { Minimum instruction execution time: 59 ns (@ 17 MHz operation with main system clock (fXX)) 50 ns (@ 20 MHz operation with main system clock (fXX)) 30.
5 µs (@ 32.
768 kHz operation with subsystem clock (fXT)) { General-purpose registers: 32 bits × 32 registers { Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { Memory space: 16 MB linear address space Memory block allocation function: 2 MB per block { External bus interface: 16-bit data bus Address bus: Separate output enabled { Internal memory Mask ROM: 64 KB (µPD703014A, 703014AY) 128 KB (µPD703015A, 703015AY) 256 KB (µPD703017A, 703017AY) RAM: 4 KB (µPD703014A, 703014AY, 703...



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