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PCK2510S

Part Number	PCK2510S
Manufacturer	NXP
Description	50-150 MHz 1:10 SDRAM clock driver
Published	Mar 22, 2005
Detailed Description	INTEGRATED CIRCUITS PCK2510S 50–150 MHz 1:10 SDRAM clock driver Product specification 1999 Dec 13 Philips Semiconducto...
Datasheet	PCK2510S PDF File

Overview

INTEGRATED CIRCUITS PCK2510S 50–150 MHz 1:10 SDRAM clock driver Product specification 1999 Dec 13 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510S FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications independent of the duty cycle at CLK.
All outputs can be enabled or disabled via a single output enable input.
When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the PCK2510S does not require external RC networks.
The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2510S requires a stabilization time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference.
The PLL can be bypassed for test purposes by strapping AVCC to ground.
The PCK2510S is characterized for operation from 0°C to +70°C.
• Spread Spectrum clock compatible • Operating frequency 50 to 150 MHz • (tphase error – jitter) at 100 to133 MHz = ±50 ps • Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps • Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps • Pin-to-pin skew < 200 ps • Available in plastic 24-Pin TSSOP • Distributes one clock input to one bank of ten outputs • External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input PIN CONFIGURATION AGND VCC 1Y0 1Y1 1Y2 GND 1 2 3 4 5 6 7 8 9 24 CLK 23 AVCC 22 VCC 21 1Y9 20 1Y8 19 GND 18 GND 17 1Y7 16 1Y6 15 1Y5 14 VCC 13 FBIN • On-Chip series damping resistors • No external RC network required • Operates at 3.
3 V DESCRIPTION The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.
It uses a PLL...

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