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ZNBG3110

Zetex Semiconductors
Part Number ZNBG3110
Manufacturer Zetex Semiconductors
Description FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION
Published Apr 17, 2005
Detailed Description FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION ISSUE 2 - APRIL 1998 DEVICE DESCRIPTION The ZNBG series ...
Datasheet PDF File ZNBG3110 PDF File

ZNBG3110
ZNBG3110

Overview
FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION ISSUE 2 - APRIL 1998 DEVICE DESCRIPTION The ZNBG series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs, PMR cellular telephones etc.
with a minimum of external components.
With the addition of two capacitors and a resistor the devices provide drain voltage and current control for three external grounded source FETs, generating the regulated negative rail required for FET gate biasing whilst operating from a single supply.
This negative bias, at -3 volts, can also be used to supply other external circuits.
The ZNBG3110/11 includes bias circuits to drive up to three external FETs.
A control input to the device selects either one of two FETs as operational, the third FET is p e r m a n e n t l y a ct i v e .
T hi s f e a t u r e i s particularly used as an LNB polarisation switch.
Also specific to LNB applications is the 22KHz tone detection and logic output feature which is used to enable high and low band frequency switching.
Drain current setting of the ZNBG3110/11 is user selectable over the range 0 to 15mA, this is achieved with addition of a single resistor.
The series also offers the choice of drain voltage to be set for the FETs, the 3110 gives 2.
2 volts drain whilst the 3111 gives 2 volts.
ZNBG3110 ZNBG3111 These devices are unconditionally stable over the full working temperature with the FETs in place, subject to the inclusion of the recommended gate and drain capacitors.
These ensure RF stability and minimal injected noise.
It is possible to use less than the devices full complement of FET bias controls, unused drain and gate connections can be left open circuit without affecting operation of the remaining bias circuits.
In order to protect the external FETs the circuits have been designed to ensure that, under any conditions including power up/down transients, the gate drive from the bias circuits cannot exceed the range -...


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