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IDT74FCT2646AT

Integrated Device Tech
Part Number IDT74FCT2646AT
Manufacturer Integrated Device Tech
Description FAST CMOS OCTAL TRANSCEIVER/REGISTERS
Published Apr 21, 2005
Detailed Description FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) Integrated Device Technology, Inc. IDT54/74FCT646T/AT/CT/DT - 2646T/AT...
Datasheet PDF File IDT74FCT2646AT PDF File

IDT74FCT2646AT
IDT74FCT2646AT

Overview
FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) Integrated Device Technology, Inc.
IDT54/74FCT646T/AT/CT/DT - 2646T/AT/CT IDT54/74FCT648T/AT/CT IDT54/74FCT652T/AT/CT/DT - 2652T/AT/CT FEATURES: • Common features: – Low input and output leakage ≤1µA (max.
) – Extended commercial range of –40°C to +85°C – CMOS power levels – True TTL input and output compatibility – VOH = 3.
3V (typ.
) – VOL = 0.
3V (typ.
) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, TSSOP, CERPACK and LCC packages • Features for FCT646T/648T/652T: – Std.
, A, C and D speed grades – High drive outputs (-15mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” • Features for FCT2646T/2652T: – Std.
, A, and C speed grades – Resistor outputs (-15mA IOH, 12mA IOL Com.
) (-12mA IOH, 12mA IOL Mil.
) – Reduced system switching noise DESCRIPTION: The FCT646T/FCT2646T/FCT648T/FCT652T/2652T consist of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
The FCT652T/FCT2652T utilize GAB and GBA signals to control the transceiver functions.
The FCT646T/FCT2646T/ FCT648T utilize the enable control (G) and direction (DIR) pins to control the transceiver functions.
SAB and SBA control pins are provided to select either realtime or stored data transfer.
The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and realtime data.
A LOW input level selects real-time data and a HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control...


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