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74HCT7273

Philips
Part Number 74HCT7273
Manufacturer Philips
Description Octal D-type flip-flop
Published Apr 23, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET 74HCT7273 Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs ...
Datasheet PDF File 74HCT7273 PDF File

74HCT7273
74HCT7273

Overview
INTEGRATED CIRCUITS DATA SHEET 74HCT7273 Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs Product specification File under Integrated Circuits, IC06 1999 Oct 01 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs FEATURES • ESD protection: HBM EIA/JESD22-A114-A Exceeds 2000 V MM EIA/JESD22-A115-A Exceeds 200 V • Ideal buffer for MOS microprocessor or memory • Eight positive edge-triggered D-type flip-flops • Common clock and master reset • Output capability: standard (open drain) • ICC category: MSI.
DESCRIPTION 74HCT7273 The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no 7A.
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.
The common Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
A LOW level on the MR input forces all outputs LOW, independently of the clock or data inputs.
The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode connected to VCC.
When a HIGH is clocked in the flip-flop, the output comes in the high-impedance OFF-state.
The output may now be pulled to any voltage between GND and VOmax.
This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter.
For digital operation and OR-tied output applications, the device must have a pull-up resistor to establish a logic HIGH level.
QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf = 6.
0 ns.
SYMBOL tPZL/tPLZ CP to Qn MR to Qn fmax CI CPD Notes 1.
CPD is used to determine the dynamic po...


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