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TC74VHCT74AF

Toshiba
Part Number TC74VHCT74AF
Manufacturer Toshiba
Description Dual D-Type Flip-Flop
Published Apr 23, 2005
Detailed Description TC74VHCT74AF/AFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT74AF, TC74VHCT74AFT Dual D-Type Fli...
Datasheet PDF File TC74VHCT74AF PDF File

TC74VHCT74AF
TC74VHCT74AF

Overview
TC74VHCT74AF/AFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT74AF, TC74VHCT74AFT Dual D-Type Flip-Flop with Preset and Clear The TC74VHCT74 is an advanced high speed CMOS D-TYPE FLIP –FLOP fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse.
CLR and PR are independent of the CK and are accomplished by setting the appropriate input low.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.
3 V to 5 V system.
Input protection and output circuit ensure that 0 to 5.
5 V can be applied to the input and output (Note) pins without regard to the supply voltage.
These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc.
TC74VHCT74AF TC74VHCT74AFT Note: VCC = 0 V Features Weight SOP14-P-300-1.
27A: 0.
18 g (typ.
) TSSOP14-P-0044-0.
65A: 0.
06 g (typ.
) • High speed: fmax = 160 MHz (typ.
) at VCC = 5 V • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C • Compatible with TTL inputs: VIL = 0.
8 V (max) VIH = 2.
0 V (min) • Power down protection is provided on all inputs and outputs • Balanced propagation delays: tpLH ≈ tpHL • Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.
) 74 type.
Start of commercial production 1995-12 1 2014-03-01 Pin Assignment TC74VHCT74AF/AFT IEC Logic Symbol 1CLR 1 1D 2 1CK 3 1PR 4 1Q 5 1Q 6 GND 7 CK D QQ CK D QQ 14 VCC 13 2CLR 12 2D 11 2CK 10 2PR 9 2Q 8 2Q 1PR (4) 1CK (3) 1D (2) 1CLR (1) 2PR (10) 2CK (11) 2D (12) 2CLR (13) S C1 1D R (5) 1Q (6) 1Q (9) 2Q (8) 2Q (top view) Truth Table CLR L H L H H H Inputs PR D H X L X L X H L H H H X X: Don’t care Outputs CK Q Q Function X L H C...


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