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TC7MZ138FK

Toshiba
Part Number TC7MZ138FK
Manufacturer Toshiba
Description Low Voltage 3-to-8 Line Decoder
Published Apr 23, 2005
Detailed Description TC7MZ138FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7MZ138FK Low Voltage 3-to-8 Line Decoder with 5 ...
Datasheet PDF File TC7MZ138FK PDF File

TC7MZ138FK
TC7MZ138FK


Overview
TC7MZ138FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7MZ138FK Low Voltage 3-to-8 Line Decoder with 5 V Tolerant Inputs and Outputs The TC7MZ138FK is a high performance CMOS 3-to-8 decoder.
Designed for use in 3.
3 V systems, it achieves high speed operation while maintaining the CMOS low power dissipation.
The device is designed for low-voltage (3.
3 V) VCC applications, but it could be used to interface to 5 V supply environment for inputs.
When the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go low.
When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high.
G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems.
All inputs are equipped with protection circuits against static discharge.
Weight: 0.
02 g (typ.
) Features • Low voltage operation: VCC = 2.
0~3.
6 V • High speed operation: tpd = 6.
0 ns (max) (VCC = 3.
0~3.
6 V) • Output current: |IOH|/IOL = 24 mA (min) (VCC = 3.
0 V) • Latch-up performance: −500 mA • Package: VSSOP (US16) • Power down protection is provided on all inputs and outputs.
• Pin and function compatible with the 74 series (74AC/VHC/HC/F/ALS/LS etc.
) 138 type.
1 2007-10-19 Pin Assignment (top view) TC7MZ138FK A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 IEC Logic Symbol 1 A 2 B 3 C 6 G1 4 G2A 5 G2B Bin/Oct 15 1 0 Y0 14 2 1 Y1 13 4 2 Y2 12 3 Y3 & 11 4 Y4 10 5 Y5 9 EN 6 Y6 7 7 Y7 1 A 2 B 3 C 6 G1 4 G2A 5 G2B Dmux 15 0 0 Y0 0 G 2 7 14 1 Y1 13 2 Y2 12 3 Y3 & 11 4 Y4 10 5 Y5 9 6 Y6 7 7 Y7 Truth Table Inputs Enable Select G1 G2A G2B C B A LXXXXX XHXXXX XXHXXX H L L L L L H L L L L H H L L L H L H L L L H H H L L H L L H L L H L H H L L H H L H L L H H H Outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 HH...


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