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LMU217

Part Number	LMU217
Manufacturer	LOGIC Devices Incorporated
Description	16 x 16-bit Parallel multiplier
Published	Apr 25, 2005
Detailed Description	LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel multipl...
Datasheet	LMU217 PDF File

Overview

LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel multiplier DESCRIPTION The LMU217 is a high-speed, low RND is loaded on the rising edge of power 16-bit parallel multiplier.
CLK, provided either ENA or ENB are LOW.
RND, when HIGH, adds ‘1’ to The LMU217 produces the 32-bit prodthe most significant bit position of the uct of two 16-bit numbers.
Data present least significant half of the product.
at the A inputs, along with the TCA Subsequent truncation of the 16 least control bit, is loaded into the A register significant bits produces a result on the rising edge of CLK.
B data and correctly rounded to 16-bit precision.
the TCB control bit are similarly loaded.
Loading of the A and B At the output, the Right Shift control registers is controlled by the ENA and (RS) selects either of two output formats.
ENB controls.
When HIGH, these con- RS LOW produces a 31-bit product trols prevent application of the clock to with a copy of the sign bit inserted in the the respective register.
The TCA and MSB postion of the least significant half.
TCB controls specify the operands as RS HIGH gives a full 32-bit product.
Two two’s complement when HIGH, or 16-bit output registers are provided to unsigned magnitude when LOW.
hold the most and least significant halves of the result (MSP and LSP) as defined by RS.
These registers are loaded on the rising edge of CLK, subject to the ENR control.
When ENR is B 15-0/ HIGH, clocking of the result registers is R 15-0 prevented.
A 15-0 TCB 16 A REGISTER 16 B REGISTER FEATURES u 25 ns Worst-Case Multiply Time u Low Power CMOS Technology u Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 u Single Clock Architecture with Register Enables u Two’s Complement, Unsigned, or Mixed Operands u Three-State Outputs u 68-pin PLCC, J-Lead LMU217 BLOCK DIAGRAM TCA CLK ENA ENB For asynchronous output, these registers may be made transparent by setting the feed through control (FT) HIGH an...

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