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MC100H602

ON Semiconductor
Part Number MC100H602
Manufacturer ON Semiconductor
Description 9-Bit Latch TTL/ECL Translator
Published Apr 26, 2005
Detailed Description www.DataSheet4U.com MC10H602, MC100H602 9−Bit Latch TTL to ECL Translator Description The MC10H/100H602 is a 9−bit, du...
Datasheet PDF File MC100H602 PDF File

MC100H602
MC100H602

Overview
www.
DataSheet4U.
com MC10H602, MC100H602 9−Bit Latch TTL to ECL Translator Description The MC10H/100H602 is a 9−bit, dual supply TTL to ECL translator with latch.
Devices in the ON Semiconductor 9−bit translator series utilize the PLCC−28 for optimal power pinning, signal flow−through and electrical performance.
The H602 features D−type latches.
Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches.
A post−latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data.
All control inputs are ECL level.
The 10H version is compatible with MECL 10Ht ECL logic levels.
The 100H version is compatible with 100K levels.
Features http://onsemi.
com PLCC−28 FN SUFFIX CASE 776 • 9−Bit Ideal for Byte−Parity Applications • Flow−Through Configuration • Extra TTL and ECL Power/Ground Pins to Minimize • • • • Switching Noise Dual Supply 3.
5 ns Max D to Q PNP TTL Inputs for Low Loading Pb−Free Packages are Available* MARKING DIAGRAM* 1 MCxxxH602G AWLYYWW xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev.
10 1 Publication Order Number: MC10H602/D MC10H602, MC100H602 D5 D4 VCCT D3 25 24 23 22 D2 D1 D0 21 20 19 18 17 16 15 Table 1.
PIN NAMES Q0 Q1 VCCE VCCO Q2 VCCO Q3 D6 D7 D8 GND MR LEN ENECL 26 27 28 PIN GND VCCE VCCO VCCT VEE D0 − D8 Q0 − Q8 ENECL LEN MR FUNCTION TTL Ground (0 V) ECL VCC (0 V) ECL VCC (0 V) — Outputs TTL Supply (+ 5.
0 V) ECL Supply (− 5.
2 / − 4.
5 V) Data Inputs (TTL) ...


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