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MC100LVEP111

Part Number	MC100LVEP111
Manufacturer	ON Semiconductor
Description	2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver
Published	Apr 26, 2005
Detailed Description	MC100LVEP111 2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 2:1:...
Datasheet	MC100LVEP111 PDF File

Overview

MC100LVEP111 2.
5V / 3.
3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 2:1:10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer.
The PECL input signals can be either differential or single−ended (if the VBB output is used).
HSTL inputs can be used when the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and from device to device.
To ensure tightest skew, both sides of differential outputs identically terminate into 50 W even if only one output is being use...

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