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MC10E416

ON Semiconductor
Part Number MC10E416
Manufacturer ON Semiconductor
Description QUINT DIFFERENTIAL LINE RECEIVER
Published Apr 26, 2005
Detailed Description www.DataSheet4U.com MC10E416, MC100E416 5V ECL Quint Differential Line Receiver Description The MC10E416/100E416 is a ...
Datasheet PDF File MC10E416 PDF File

MC10E416
MC10E416

Overview
www.
DataSheet4U.
com MC10E416, MC100E416 5V ECL Quint Differential Line Receiver Description The MC10E416/100E416 is a 5-bit differential line receiving device.
The 2.
0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state.
Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device.
Note that the input clamp will take affect only if both inputs fall 2.
5 V below VCC.
The VBB pin, an internally generated voltage supply, is available to this device only.
For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs.
When used, decouple VBB and VCC via a 0.
01 mF capacitor and limit current sourcing or sinking to 0.
5 mA.
When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features http://onsemi.
com PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 28 MCxxxE416FNG AWLYYWW • • • • • • Differential D and Q; VBB available 600 ps Max.
Propagation Delay High Frequency Outputs 2 Stages of Gain PECL Mode Operating Range: VCC = 4.
2 V to 5.
7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.
2 V to −5.
7 V Internal Input 50 kW Pulldown Resistors Machine Model; > 200 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
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