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MC14001UB

ON Semiconductor
Part Number MC14001UB
Manufacturer ON Semiconductor
Description UB-Suffix Series CMOS Gates
Published Apr 26, 2005
Detailed Description MC14001UB, MC14011UB UB-Suffix Series CMOS Gates The UB Series logic gates are constructed with P and N channel enhance...
Datasheet PDF File MC14001UB PDF File

MC14001UB
MC14001UB

Overview
MC14001UB, MC14011UB UB-Suffix Series CMOS Gates The UB Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS).
Their primary use is where low power dissipation and/or high noise immunity is desired.
The UB set of CMOS gates are inverting non−buffered functions.
Features • Supply Voltage Range = 3.
0 Vdc to 18 Vdc • Linear and Oscillator Applications • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Double Diode Protection on All Inputs • Pin−for−Pin Replacements for Corresponding CD4000 Series UB Suffix Devices • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD Vin, Vout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) −0.
5 to +18.
0 −0.
5 to VDD + 0.
5 V V Iin, Iout Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device.
If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1.
Temperature Derating: “D/DW” Package: –7.
0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit.
For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an...


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