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MC14012B

ON Semiconductor
Part Number MC14012B
Manufacturer ON Semiconductor
Description Dual 4-Input NAND Gates
Published Apr 26, 2005
Detailed Description MC14012B Dual 4-Input NAND Gates The MC14012B dual 4−input NAND gates are constructed with P−Channel and N−Channel enha...
Datasheet PDF File MC14012B PDF File

MC14012B
MC14012B


Overview
MC14012B Dual 4-Input NAND Gates The MC14012B dual 4−input NAND gates are constructed with P−Channel and N−Channel enhancement mode devices in a single monolithic structure (Complementary MOS).
Their primary use is where low power dissipation and/or high noise immunity is desired.
Features • Supply Voltage Range = 3.
0 Vdc to 18 Vdc • All Outputs Buffered • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Double Diode Protection on All Inputs • Pin−for−Pin Replacements for Corresponding CD4000 Series B Suffix Devices • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD Vin, Vout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) −0.
5 to +18.
0 −0.
5 to VDD + 0.
5 V V Iin, Iout Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device.
If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1.
Temperature Derating: “D/DW” Package: –7.
0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit.
For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.
g.
, either VSS or VDD).
Unused outputs ...


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