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M54HCT273

ST Microelectronics
Part Number M54HCT273
Manufacturer ST Microelectronics
Description OCTAL D TYPE FLIP FLOP WITH CLEAR
Published Apr 26, 2005
Detailed Description M54HCT273 M74HCT273 OCTAL D TYPE FLIP FLOP WITH CLEAR . . . . . . . HIGH SPEED fMAX = 80 MHz (TYP.) AT VCC = 5 V LOW P...
Datasheet PDF File M54HCT273 PDF File

M54HCT273
M54HCT273

Overview
M54HCT273 M74HCT273 OCTAL D TYPE FLIP FLOP WITH CLEAR .
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HIGH SPEED fMAX = 80 MHz (TYP.
) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.
) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.
) VIL = 0.
8V (MAX) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.
) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS273 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) DESCRIPTION The M54/74HCT273 is a high speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated in sili2 con gate C MOS technology.
It has the same high speed performance of LSTTL combined with true CMOS low power consumption.
Information signals applied to D inputs are transferred to the Q outputs on the positive-going edge of the clock pulse.
When the CLEAR input is held low, the Q output are in the low logic level independent of the other inputs.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families.
M54/74HCT devices are de2 signed to directly interface HSC MOS systems with TTL and NMOS components.
They are also plug in replacements for LSTTL devices giving a reduction of power consumption.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT ORDER CODES : M54HCT273F1R M74HCT273M1R M74HCT273B1R M74HCT273C1R PIN CONNECTIONS (top view) NC = No Internal Connection February 1993 1/10 M54/M74HCT273 PIN DESCRIPTION PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL CLEAR Q0 to Q7 NAME AND FUNCTION Master Reset Input (Active LOW) Flip Flop Outputs IEC LOGIC SYMBOL D0 to D7 Data Inputs CLOCK GND V CC Clock Input (LOW to HIGH, Edge Triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE CLEAR...


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