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M5M4V64S40ATP-8L

Mitsubishi
Part Number M5M4V64S40ATP-8L
Manufacturer Mitsubishi
Description 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Published Apr 26, 2005
Detailed Description SDRAM (Rev.1.3) Mar'98 MITSUBISHI LSIs M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchro...
Datasheet PDF File M5M4V64S40ATP-8L PDF File

M5M4V64S40ATP-8L
M5M4V64S40ATP-8L

Overview
SDRAM (Rev.
1.
3) Mar'98 MITSUBISHI LSIs M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Some of contents are subject to change without notice.
DESCRIPTION The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit Synchronous DRAM, with LVTTL interface.
All inputs and outputs are referenced to the rising edge of CLK.
The M5M4V64S40ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.
Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 Vdd PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC (Vref) DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss FEATURES - Single 3.
3v±0.
3v power supply - Clock frequency 125MHz /100MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/Full Page (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Burst Write / Single Write (programmable) - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A7 - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.
8mm lead pitch Max.
Frequency M5M4V64S40ATP-8A M5M4V64S40ATP-8 M5M4V64S40ATP-10 125MHz 100MHz 100MHz CLK Access Time 6ns 6ns 8ns CLK CKE /CS /RAS /CAS /WE DQ0-15 DQML/U A0-11 BA0,1 Vdd VddQ Vss VssQ : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output 400mil 54pin TSO...


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