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M5M54R16AJ-15

Mitsubishi
Part Number M5M54R16AJ-15
Manufacturer Mitsubishi
Description 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Published Apr 26, 2005
Detailed Description 1998.11.30 Ver.B MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are sub...
Datasheet PDF File M5M54R16AJ-15 PDF File

M5M54R16AJ-15
M5M54R16AJ-15

Overview
1998.
11.
30 Ver.
B MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification.
Some parametric limits are subject to change.
M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R16A is a family of 262144-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application.
These devices operate on a single 3.
3V supply, and are directly TTL compatible.
They include a power down feature as well.
In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by LB and UB.
CHIP SELECT INPUT DATA INPUTS/ OUTPUTS ADDRESS INPUTS PIN CONFIGURATION (TOP VIEW) FEATURES •Fast access time M5M54R16AJ,ATP-10 .
.
.
10ns(max) M5M54R16AJ,ATP-12 .
.
.
12ns(max) M5M54R16AJ,ATP-15 .
.
.
15ns(max) A0 A1 A2 A3 A4 S DQ1 DQ2 DQ3 DQ4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 •Single +3.
3V power supply •Fully static operation : No clocks, No refresh •Common data I/O •Easy memory expansion by S •Three-state outputs : OR-tie capability •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs •Separate control of lower and upper bytes by LB and UB GND DQ5 DATA DQ6 INPUTS/ DQ7 OUTPUTS DQ8 WRITE CONTROL INPUT W A5 A6 ADDRESS INPUTS A7 A8 A9 (3.
3V) (0V) VCC A17 ADDRESS A16 INPUTS A15 OUTPUT OE ENABLE INPUT BYTE UB CONTROL LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V) VCC DQ12 DQ11 DQ10 DQ9 N.
C A14 A13 A12 A11 A10 (3.
3V) DATA INPUTS/ OUTPUTS ADDRESS INPUTS Outline 44P0K APPLICATION High-speed memory system PACKAGE M5M54R16AJ 44pin 400mil SOJ M5M54R16ATP 44pin 400mil TSOP(II) state.
(LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-select...


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