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MACH110-12

Part Number	MACH110-12
Manufacturer	Lattice
Description	High-Density EE CMOS Programmable Logic
Published	Apr 27, 2005
Detailed Description	FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERI...
Datasheet	MACH110-12 PDF File

Overview

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD Industrial s 77 MHz fCNT s 38 Inputs s 32 Outputs Lattice Semiconductor s 32 Flip-flops; 2 clock choices s 2 “PAL22V16” Blocks s Pin-compatible with MACH111, MACH210, MACH211, MACH215 GENERAL DESCRIPTION The MACH110 is a member of our high-performance EE CMOS MACH 1 family.
This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed.
The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix.
The two PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells.
The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
The MACH110 macrocell provides either registered or combinatorial outputs with programmable polarity.
If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms.
The register type decision can be made by the designer or by the software.
All macrocells can be connected to an I/O cell.
If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.
Publication# 14127 Rev.
I Issue Date: May 1995 Amendment /0 BLOCK DIAGRAM I/O0 – I/O15 I0 – I1, I3 – I4 16 16 I/O Cells 16 16 2 Macrocells OE 44 x 70 AND Logic Array and Logic Allocator 4 22 Switch Matrix 22 44 x 70 AND Logic Array and Logic Allocator OE 2 Macrocells 16 I/O Cells 16 16 16 2 2 I/O16 – I/O31 CLK1/I5, CLK0/I2 14127I-1 2 MACH110-12/15/20 CONNECTION DIAGRAM Top View PLCC I/O31 I/O30 I/O29 I/O28 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26...

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