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MACH120-12

Lattice
Part Number MACH120-12
Manufacturer Lattice
Description High-Performance EE CMOS Programmable Logic
Published Apr 27, 2005
Detailed Description 1 FINAL MACH 1 & 2 FAMILIES COM’L: -12/15 IND: -18 Lattice Semiconductor MACH120-12/15 High-Performance EE CMOS Pro...
Datasheet PDF File MACH120-12 PDF File

MACH120-12
MACH120-12

Overview
1 FINAL MACH 1 & 2 FAMILIES COM’L: -12/15 IND: -18 Lattice Semiconductor MACH120-12/15 High-Performance EE CMOS Programmable Logic MACH 1 & 2 Families DISTINCTIVE CHARACTERISTICS x 68 Pins in PLCC x 48 Macrocells x 12 ns tPD Commercial, 18 ns tPD Industrial x x x x x x x 77 MHz fCNT Commercial 48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks 48 Outputs 48 Flip-flops; 4 clock choices 4 “PALCE26V12” blocks SpeedLocking™ for guaranteed fixed timing Pin-compatible with the MACH221 GENERAL DESCRIPTION The MACH120 is a member of the high-performance EE CMOS MACH ® 1 family.
This device has approximately five times the logic macrocell capability of the popular PALCE22V10 without loss of speed.
The MACH120 consists of four PAL® blocks interconnected by a programmable switch matrix.
The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
The MACH120 macrocell provides either registered or combinatorial outputs with programmable polarity.
If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms.
The register type decision can be made by the designer or by the software.
All macrocells can be connected to an I/O cell.
If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.
Publication# 14129 Amendment/0 Rev: J Issue Date: November 1997 BLOCK DIAGRAM Block A I/O0–I/O11 12 I/O Cells 12 Macrocells OE 52 x 54 AND Logic Array and Logic Allocator 26 Switch Matrix OE 52 x 54 AND Logic Array and Logic Allocator 26 Macrocells 4 I/O Cells 12 4 Block B I/O12–I/O23 12 I2–I3 I6–I7 MACH 1 & 2 Families 26 52 x 54 AND Logic Array and Logic Allocator OE Macrocells 12 I/O Cells 12 26 52 x 54 AND Logic Array and Logic Allocator OE Macrocells 12 I/O Cells 12 4 4 I...


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