DatasheetsPDF.com

PI74ALVCH16823

Pericom Semiconductor Corporation
Part Number PI74ALVCH16823
Manufacturer Pericom Semiconductor Corporation
Description 18-Bit Bus-Interface Flip-Flop with 3-State Outputs
Published Mar 22, 2005
Detailed Description 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234...
Datasheet PDF File PI74ALVCH16823 PDF File

PI74ALVCH16823
PI74ALVCH16823

Overview
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74ALVCH16823 18-Bit Bus-Interface Flip-Flop with 3-State Outputs Product Features • PI74ALVCH16823 is designed for low voltage operation • VCC = 2.
3V to 3.
6V • Hysteresis on all inputs • Typical VOLP (Output Ground Bounce) < 0.
8V at VCC = 3.
3V, TA = 25°C • Typical VOHV (Output VOH Undershoot) < 2.
0V at VCC = 3.
3V, TA = 25°C • Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors • Industrial operation at –40°C to +85°C • Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) Product Description Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.
5 micron CMOS technology, achieving industry leading speed.
The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed for 2.
3V to 3.
6V VCC operation.
It features 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads.
This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The PI74ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop.
With the Clock Enable (CLKEN) input LOW, the D-type flip-flops enter data on the low-to-high transitions of the clock.
Taking CLKEN HIGH disables the clock buffer, thus latching the outputs.
Taking the Clear (CLR) input LOW causes the Q outputs to go LOW independently of the clock.
A buffered Output Enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines ...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)