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74LVC646A

NXP
Part Number 74LVC646A
Manufacturer NXP
Description Octal bus transceiver/register
Published Mar 22, 2005
Detailed Description 74LVC646A Octal bus transceiver/register; 3-state Rev. 5 — 28 March 2013 Product data sheet 1. General description The...
Datasheet PDF File 74LVC646A PDF File

74LVC646A
74LVC646A

Overview
74LVC646A Octal bus transceiver/register; 3-state Rev.
5 — 28 March 2013 Product data sheet 1.
General description The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers.
Data on the A or B bus is clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level.
Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function.
In the transceiver mode, data present at the high-impedance port may be stored in either the A or B register, or in both.
With the select source inputs (SAB and SBA), stored and real-time (transparent mode) data can be multiplexed.
The direction (DIR) input determines which bus receives data when OE is active (LOW).
In the isolation mode (OE = HIGH), A data may be stored in the B register and/or B data may be stored in the A register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit data.
Only one of the two buses A or B may be driven at a time.
Inputs can be driven from either 3.
3 V or 5 V devices.
When disabled, up to 5.
5 V can be applied to the outputs.
These features allow the use of these devices as translators in mixed 3.
3 V and 5 V applications.
2.
Features and benefits  5 V tolerant inputs/outputs for interfacing with 5 V logic  Supply voltage range from 1.
2 V to 3.
6 V  CMOS low-power consumption  Direct interface with TTL levels  8-bit octal transceiver with D-type latch  Back-to-back registers for storage  Separate controls for data flow in each direction  Supports partial power-down applications; inputs/outputs are high-impedance when VCC = 0 V  Complies with JEDEC standard:  JESD8-7A (1.
65 V to 1.
95 V)  JESD8-5A (2.
3 V to 2.
7 V)  JESD8-C/JESD36 (2.
7 V to 3.
6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds ...


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