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MCM6323A

Motorola
Part Number MCM6323A
Manufacturer Motorola
Description 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM
Published Apr 30, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6323A/D Product Preview MCM6323A 64K x 16 Bit 3.3 V...
Datasheet PDF File MCM6323A PDF File

MCM6323A
MCM6323A

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6323A/D Product Preview MCM6323A 64K x 16 Bit 3.
3 V Asynchronous Fast Static RAM The MCM6323A is a 1,048,576 bit static random access memory organized as 65,536 words of 16 bits.
Static design eliminates the need for external clocks or timing strobes; CMOS circuitry reduces power consumption and provides for greater reliability.
The MCM6323A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems.
Separate byte enable controls (LB and UB) allow individual bytes to be written and read.
LB controls the 8 DQa bits, while UB controls the 8 DQb bits.
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) package and a 44–lead TSOP Type II package in copper leadframe for optimum printed circuit board (PCB) reliability.
• • • • • • • • Single 3.
3 V ± 0.
3 V Power Supply Fast Access Time: 10, 12, 15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Data Byte Control Fully Static Operation Power Operation: 140/135/130 mA Maximum, Active AC Industrial Temperature Option: – 40 to + 85°C Part Number: SCM6323AYJ10A BLOCK DIAGRAM G OUTPUT ENABLE BUFFER 7 ADDRESS BUFFERS 9 ROW COLUMN DECODER DECODER 8 HIGH BYTE OUTPUT ENABLE LOW BYTE OUTPUT ENABLE 8 HIGH BYTE OUTPUT BUFFER HIGH BYTE WRITE DRIVER 8 DQb 8 YJ PACKAGE 400 MIL SOJ CASE 919–01 TS PACKAGE 44–LEAD TSOP TYPE II CASE 924A–01 PIN ASSIGNMENT A A A A A E DQa DQa DQa DQa VDD VSS DQa DQa DQa DQa W A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A A A G UB LB DQb DQb DQb DQb VSS VDD DQb DQb DQb DQb NC A A A A NC A 16 E CHIP ENABLE BUFFER 64K x 16 BIT MEMORY ARRAY 16 SENSE AMPS 8 8 A A NC W WRITE ENABLE BUFFER LOW BYTE OUTPUT BUFFER 8 LOW BYTE WRITE DRIVER 8 DQa 8 PIN NAMES A .
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