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MCM63F733A

Motorola
Part Number MCM63F733A
Manufacturer Motorola
Description 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
Published Apr 30, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63F733A/D Advance Information MCM63F733A 128K x 32 ...
Datasheet PDF File MCM63F733A PDF File

MCM63F733A
MCM63F733A

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63F733A/D Advance Information MCM63F733A 128K x 32 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM63F733A is a 4M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors.
It is organized as 128K words of 32 bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications.
Synchronous design allows precise cycle control with the use of an external clock (K).
CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and Linear Burst Order (LBO) are clock (K) controlled through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins.
Subsequent burst addresses can be generated internally by the MCM63F733A (burst sequence operates in linear or interleaved mode dependent upon state of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input.
This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes.
The four bytes are designated as “a”, “b”, “c”, and “d”.
SBa controls DQa, SBb controls DQb, etc.
Individual bytes are written if the selected byte writes SBx are asserted with SW.
All bytes are written if either SGW is asserted or if all SBx and SW are asserted.
For read cycles, a flow–through ...


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