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MCM6706BR

Part Number	MCM6706BR
Manufacturer	Motorola
Description	32K x 8 Bit Static Random Access Memory
Published	Apr 30, 2005
Detailed Description	MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6706BR/D Product Preview MCM6706BR 32K x 8 Bit Stat...
Datasheet	MCM6706BR PDF File

Overview

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6706BR/D Product Preview MCM6706BR 32K x 8 Bit Static Random Access Memory The MCM6706BR is a 262,144 bit static random access memory organized as 32,768 words of 8 bits.
Static design eliminates the need for external clocks or timing strobes.
Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems.
The MCM6706BR meets JEDEC standards and is available in a revolutionary pinout 300 mil, 32–lead surface–mount SOJ package.
• • • • • Single 5.
0 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary All Inputs and Outputs Are TTL Compatible Three State Outputs Fast Access Times: MCM6706BR–6 = 6 ns MCM6706BR–7 = 7 ns MCM6706BR–8 = 8 ns • Center Power and I/O Pins for Reduced Noise BLOCK DIAGRAM A A A A A A A A A ROW DECODER MEMORY MATRIX 512 ROWS x 64 x 8 COLUMNS VCC VSS J PACKAGE 300 MIL SOJ CASE 857–02 PIN ASSIGNMENT A A A A E DQ DQ VCC VSS DQ DQ W A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A A A G DQ DQ VSS VCC DQ DQ A A A A NC PIN NAMES D0 INPUT DATA CONTROL DQ A COLUMN I/O COLUMN DECODER A .
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Address W .
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Write Enable E .
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Chip Enable G .
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Output Enable DQ .
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Data Input/Output VCC .
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+ 5 V Power Supply VSS .
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Ground NC .
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No Connection A A A A A E W G This document contains information on a new product under development.
Motorola reserves the right to change or discontinue this product without notice.
REV 1 10/9/96 © Motorola, Inc.
1996 MOTOROLA FAST SRAM MCM6706BR 1 TRUTH TABLE E H L L L G X H L ...

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