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MCM67T415

Motorola
Part Number MCM67T415
Manufacturer Motorola
Description 16K x 15 Bit Cache Tag RAM for Pentium Processors
Published Apr 30, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67T415/D Advance Information MCM67T415 16K x 15 Bit...
Datasheet PDF File MCM67T415 PDF File

MCM67T415
MCM67T415

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67T415/D Advance Information MCM67T415 16K x 15 Bit Cache Tag RAM for Pentium™ Processors The MCM67T415 is a 245,760 bit cache–tag static RAM designed to support Pentium microprocessors at bus speeds up to 66 MHz.
It is organized as 16K words of 15 bits each and is fabricated using Motorola‘s high performance, silicon gate BiCMOS technology.
There are twelve common I/O tag bits and three separate I/O status bits.
A 12–bit comparator is on–chip to allow fast comparison of the 12 stored tag bits with the current tag input data.
An active high MATCH output is generated when the valid bit is true and these two groups of data are the same for a given address.
This high–speed MATCH signal, with tAVMV times as fast as 9 ns, provides the fastest possible enabling of secondary cache accesses.
The three separate I/O status bits (VALID, DIRTY, and WT) can be configured for either dedicated or generic functionality, depending on the SFUNC input pin.
With SFUNC low, the status bits are defined and used internally by the device, allowing easier determination of the validity and use of the given tag data.
SFUNC high releases the defined internal status bit usage and control, allowing users to configure the status bit information to fit their system needs.
A synchronous RESET pin, when held low at a rising clock edge, will reset all status bits in the array for easy invalidation of all tag addresses.
The MCM67T415 also provides the option for burst ready (BRDY) generation within the cache tag itself, based upon MATCH, VALID bit, WT bit, and other external inputs provided by the user.
This can significantly simplify cache controller logic and minimize cache decision time.
Match and read operations are both asynchronous in order to provide the fastest access times possible, while write operations are synchronous for ease of system timing.
The MCM67T415 uses a 5 V power supply on VCC and VSS, with separate VCCQ pins ...


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