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MCM69P819

Motorola
Part Number MCM69P819
Manufacturer Motorola
Description Pipelined BurstRAM Synchronous Fast Static RAM
Published Apr 30, 2005
Detailed Description Freescale Semiconductor, Inc... MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this docum...
Datasheet PDF File MCM69P819 PDF File

MCM69P819
MCM69P819

Overview
Freescale Semiconductor, Inc.
.
.
MOTOROLA Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69P819/D 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM MCM69P819 The MCM69P819 is a 4M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other ZP PACKAGE high performance microprocessors.
It is organized as 256K words of 18 bits C.
each.
This device integrates input registers, an output register, a 2–bit address IN counter, and high speed SRAM onto a single monolithic circuit for reduced parts R, count in cache data RAM applications.
Synchronous design allows precise cycle TO control with the use of an external clock (K).
UC Addresses (SA), data inputs (DQx), and all control signals except output D enable (G) and linear burst order (LBO) are clock (K) controlled through positive– ON edge–triggered noninverting registers.
IC Bursts can be initiated with either ADSP or ADSC input pins.
Subsequent burst EM addresses can be generated internally by the MCM69P819 (burst sequence E S operates in linear or interleaved mode dependent upon the state of LBO) and L controlled by the burst address advance (ADV) input pin.
CA Write cycles are internally self–timed and are initiated by the rising edge of the ES clock (K) input.
This feature eliminates complex off–chip write pulse generation RE and provides increased timing flexibility for incoming signals.
Y F Synchronous byte write (SBx), synchronous global write (SGW), and synchroB nous write enable (SW) are provided to allow writes to either individual bytes or ED to all bytes.
The two bytes are designated as “a” and “b”.
SBa controls DQa and IV SBb controls DQb.
Individual bytes are written if the selected byte writes SBx are CH asserted with SW.
All bytes are written if either SGW is asserted or if all SBx and AR SW are asserted.
PBGA CASE 999–02 TQ PACKAGE TQFP CASE 983A–01 For read cycles, pipelined SRAMs...


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