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M2S28D20ATP

Part Number	M2S28D20ATP
Manufacturer	Mitsubishi
Description	128M Double Data Rate Synchronous DRAM
Published	May 2, 2005
Detailed Description	DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PR...
Datasheet	M2S28D20ATP PDF File

Overview

DDR SDRAM (Rev.
0.
1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice.
DESCRIPTION M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.
All control and address signals are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK.
The M2S28D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for main memo...

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