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M378T2953BG0-CC

Part Number	M378T2953BG0-CC
Manufacturer	Samsung
Description	DDR2 Unbuffered SDRAM MODULE
Published	May 2, 2005
Detailed Description	256MB,512MB,1GB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb B-die...
Datasheet	M378T2953BG0-CC PDF File

Overview

256MB,512MB,1GB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb B-die 64/72-bit Non-ECC/ECC Revision 1.
2 January 2005 Rev.
1.
2 Jan.
2005 256MB,512MB,1GB Unbuffered DIMMs DDR2 Unbuffered DIMM Ordering Information Part Number Density Organization Component Composition Number of Rank 1 1 2 1 2 DDR2 SDRAM Height x64 Non ECC M378T3354BG(Z)0-CD5/CC M378T6553BG(Z)0-CD5/CC M378T2953BG(Z)0-CD5/CC M391T6553BG(Z)0-CD5/CC M391T2953BG(Z)0-CD5/CC 256MB 512MB 1GB 512MB 1GB 32Mx64 64Mx64 128Mx64 x72 ECC 64Mx72 128Mx72 64Mx8(K4T51083QB)*9 64Mx8(K4T51083QB)*18 30mm 30mm 32Mx16(K4T51163QB)*4 64Mx8(K4T51083QB)*8 64Mx8(K4T51083QB)*16 30mm 30mm 30mm Note: “Z” of Part number stand for Lead-free products.
Features • Performance range D5(DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK • JEDEC standard 1.
8V ± 0.
1V Power Supply • VDDQ = 1.
8V ± 0.
1V • 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin • 4 Bank • Posted CAS • Programmable CAS Latency: 3, 4, 5 • Programmable Additive Latency: 0, 1 , 2 , 3 and 4 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Average Refesh Period 7.
8us at lower then TCASE 85×C, 3.
9us at 85×C < TCASE < 95 ×C • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball FBGA - 64Mx8, 84ball FBGA - 32Mx16 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Rev.
1.
2 Jan.
2005 256MB,512MB,1GB Unbuffered DIMMs Address Configuration Organization 64Mx8(512Mb) based Module 32Mx16(512Mb) based Module DDR2 SDRAM Bank Address BA0-BA1 BA0-BA1 Row Address A0-A13 A0-A12 Column Address ...

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