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ORT4622

Agere Systems
Part Number ORT4622
Manufacturer Agere Systems
Description Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
Published May 13, 2005
Detailed Description Preliminary Data Sheet March 2000 ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backpl...
Datasheet PDF File ORT4622 PDF File

ORT4622
ORT4622


Overview
Preliminary Data Sheet March 2000 ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver Introduction Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer.
The 622 Mbits/s backplane transceiver offers a clockless, high-speed interface for interdevice communication on a board or across a backplane.
The built-in clock recovery of the ORT4622 allows for higher system performance, easier-todesign clock domains in a multiboard system, and fewer signals on the backplane.
Network designers will benefit from the backplane transceiver as a network termination device.
The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems.
For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required.
s HSI function uses Lucent Technologies Microelectronics Group’s proven 622 Mbits/s serial interface core.
Four-channel HSI function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 2.
5 Gbits/s (full duplex).
LVDS I/Os compliant with EIA*-644, support hot insertion.
8:1 data multiplexing/demultiplexing for 77.
76 MHz byte-wide data processing in FPGA logic.
On-chip phase-lock loop (PLL) clock meets B jitter tolerance specification of ITU-T Recommendation G.
958 (0.
6 UIP-P at 250 kHz).
Powerdown option of HSI receiver on a perchannel basis.
Highly efficient implementation with only 3% overhead vs.
25% for 8B10B coding.
In-Band management and configuration.
Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
Built-in boundry scan (IEEE† 1149.
1 JTAG).
FIFOs align incoming data across all four channels for STS...


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