DatasheetsPDF.com

SN74LS147

Part Number SN74LS147
Manufacturer ON Semiconductor
Title Priority Encoders
Description SN74LS147, SN74LS148 10−Line−to−4−Line and 8−Line−to−3−Line Priority Encoders The SN74LS147 and the SN74LS148 are Priority Encoders. They provide...
Features Y 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device Package Shipping SN74LS147N 16 Pin DIP 2000 Units/Box SN74LS147D SOIC−16 38 Units/Rail SN74LS147DR2 SOIC−16 2500/Tape & Reel SN74LS148N 16 Pin DIP 2000 Units/Box SN74LS148D SOIC−16 38 Units/Rail...

File Size 171.66KB
Datasheet SN74LS147 PDF File







Similar Datasheet

SN74LS14 : Each circuit in SNx414 and SNx4LS14 functions as an inverter. However, because of the Schmitt-Trigger action, they have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SOIC (14) 4.90 mm × 3.91 mm SN7414, SN74LS14 SSOP (14) PDIP (14) 6.20 mm × 5.30 mm 19.30 mm × 6.35 mm SO (14) 10.30 mm × 5.30 mm SN5414, SN54LS14 CDIP (14) CFP (14) LCCC (20) 19.56 mm × 6.67 mm 9.21 mm × 5.97 mm 8.89 mm × 8.89 mm (1) For all available packages, see the.

SN74LS14 : SN74LS14 Schmitt Triggers Dual Gate/Hex Inverter The SN74LS14 contains logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis betwe.

SN74LS14 : SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This .

SN74LS145 : SN74LS145 1−of−10 Decoder/Driver Open−Collector The SN74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is designed for use as indicator/relay drivers or as an open-collector logic circuit driver. Each of the high breakdown output transistors will sink up to 80 mA of current. Typical power dissipation is 35 mW. This device is fully compatible with all TTL families. • Low Power Version of 74145 • Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage .

SN74LS145 : SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS145, 1-of-10 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays. All outputs remain off for all invalid binary input conditions. It is designed for use as indicator/relay drivers or as an open-collector logic circuit driver. Each of the high breakdown output transistors will sink up to 80 mA of current. Typical power dissipation is 35 mW. This device is fully compatible with all TTL families. • Low Power Version of 54 / 74145 • Input Clamp Diodes Limit High Speed Termination Effects 1-OF-10 DECODER / DRIVER OPEN-COLLECTOR LOW POWER SCHOTTKY CONNECTION DIAG.

SN74LS145 : PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device 5962-8508401VEA Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP J 16 25 Eco Plan (2) TBD Lead/Ball Finish (6) A42 MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 85084012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 8508401EA 8508401FA SN54LS145J SN74145N SN74LS145D SN74LS145DG4 SN74LS145DR SN74LS145DRE4 SN74LS145N SN74LS145NE4 SN74LS145NSR SNJ54145J SNJ54LS145FK ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE CDIP CFP CDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SO CDIP LCCC J 16 1 TBD .

SN74LS145D : PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device 5962-8508401VEA Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP J 16 25 Eco Plan (2) TBD Lead/Ball Finish (6) A42 MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 85084012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 8508401EA 8508401FA SN54LS145J SN74145N SN74LS145D SN74LS145DG4 SN74LS145DR SN74LS145DRE4 SN74LS145N SN74LS145NE4 SN74LS145NSR SNJ54145J SNJ54LS145FK ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE CDIP CFP CDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SO CDIP LCCC J 16 1 .

SN74LS145N : PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device 5962-8508401VEA Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP J 16 25 Eco Plan (2) TBD Lead/Ball Finish (6) A42 MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 85084012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 8508401EA 8508401FA SN54LS145J SN74145N SN74LS145D SN74LS145DG4 SN74LS145DR SN74LS145DRE4 SN74LS145N SN74LS145NE4 SN74LS145NSR SNJ54145J SNJ54LS145FK ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE CDIP CFP CDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SO CDIP LCCC J 16 1 .

SN74LS147 : 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without n.

SN74LS147 : ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent on.

SN74LS147D : SN74LS147, SN74LS148 10−Line−to−4−Line and 8−Line−to−3−Line Priority Encoders The SN74LS147 and the SN74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allow.

SN74LS147N : SN74LS147, SN74LS148 10−Line−to−4−Line and 8−Line−to−3−Line Priority Encoders The SN74LS147 and the SN74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allow.

SN74LS148 : SN74LS147, SN74LS148 10−Line−to−4−Line and 8−Line−to−3−Line Priority Encoders The SN74LS147 and the SN74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allow.

SN74LS148 : 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without n.

SN74LS148 : ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent on.

SN74LS148D : SN74LS147, SN74LS148 10−Line−to−4−Line and 8−Line−to−3−Line Priority Encoders The SN74LS147 and the SN74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allow.




Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)