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MPC8260E

Motorola
Part Number MPC8260E
Manufacturer Motorola
Description Micro Processor
Published May 23, 2005
Detailed Description Advance Information MPC8260EC/D Rev. 0.7, 11/2001 MPC8260 (HiP3) Hardware Specifications This document contains detailed...
Datasheet PDF File MPC8260E PDF File

MPC8260E
MPC8260E

Overview
Advance Information MPC8260EC/D Rev.
0.
7, 11/2001 MPC8260 (HiP3) Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the HiP3 version of the PowerQUICC II™ MPC8260 communications processor.
The following topics are addressed: Topic Section 1.
1, “Features” Section 1.
2, “Electrical and Thermal Characteristics” Section 1.
2.
1, “DC Electrical Characteristics” Section 1.
2.
2, “Thermal Characteristics” Section 1.
2.
3, “Power Considerations” Section 1.
2.
4, “AC Electrical Characteristics” Section 1.
3, “Clock Configuration Modes” Section 1.
3.
1, “Local Bus Mode” Section 1.
4, “Pinout” Section 1.
5, “Package Description” Section 1.
6, “Ordering Information” Page 2 5 5 9 9 10 16 16 19 32 34 Features Figure 1 shows the block diagram for the MPC8260.
16 Kbytes I-Cache I-MMU G2 Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-Local Bridge Memory Controller Communication Processor Module (CPM) Clock Counter Timers Parallel I/O Baud Rate Generators 32-bit RISC Microcontroller and Program ROM 2 Virtual IDMAs Interrupt Controller 24 Kbytes Dual-Port RAM Serial DMAs System Functions 60x Bus Local Bus 32 bits, up to 66 MHz MCC1 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C Time Slot Assigner Serial Interface 8 TDM Ports 3 MII Ports 2 UTOPIA Ports Non-Multiplexed I/O Figure 1.
MPC8260 Block Diagram 1.
1 • Features Dual-issue integer core — A core version of the EC603e microprocessor — System core microprocessor supporting frequencies of 133–200 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — High-performance (4.
4–5.
1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz) — Supports bus snooping for data cache coherency — Flo...


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