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74F652 Datasheet PDF


Part Number 74F652
Manufacturer National
Title Transceivers/Registers
Description These devices consist of bus transceiver circuits with D-type flip-flops and control circuitry arranged for multiplexed transmission of data direc...
Features Y Y Y Y Independent registers for A and B buses Multiplexed real-time and stored data Choice of non-inverting and inverting data paths ’F651 inverting ’F652 non-inverting Guaranteed 4000V minimum ESD protection Commercial 74F651SPC Military Package Number N24C Package Description 24-Lead (0 30...

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74F651 : These devices consist of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. Features s Independent registers for A and B buses s Multiplexed real-time and stored data s Choice of non-inverting and inverting data paths 74F651 inverting 74F652 non-inverting Ordering Code: Order Number 74F651SC 74F651SPC 74F652SC 74F652SPC Package Number M24B N24C M24B N24C Package Description 24-Le.

74F651 : These devices consist of bus transceiver circuits with D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level Output Enable pins (OEAB OEBA) are provided to control the transceiver function Features Y Y Y Y Independent registers for A and B buses Multiplexed real-time and stored data Choice of non-inverting and inverting data paths ’F651 inverting ’F652 non-inverting Guaranteed 4000V minimum ESD protection Commercial 74F651SPC Military Package Number N24C Package Description 24-Lead (0 300 .

74F651A : The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3–State outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OEAB, OEBA) and select (SAB, SBA) pins are provided for bus management. • Independent registers for A and B buses • Multiplexed real-time and stored data • Choice of non-inverting and inverting data paths • 3-State outputs • Industrial temperature range available (–40°C to +85°C) for 74F652A TYPE 74F651/74F652 74F651A/74F652A TYPICAL fma.

74F652 : These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. Features s Independent registers for A and B buses s Multiplexed real-time and stored data s 74F652 non-inverting data path Ordering Code: Order Number 74F652SC (Note 1) 74F652SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Le.

74F652A : The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3–State outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OEAB, OEBA) and select (SAB, SBA) pins are provided for bus management. • Independent registers for A and B buses • Multiplexed real-time and stored data • Choice of non-inverting and inverting data paths • 3-State outputs • Industrial temperature range available (–40°C to +85°C) for 74F652A TYPE 74F651/74F652 74F651A/74F652A TYPICAL fma.

74F655A : The 74F655A and 74F656A are octal buffers and line drivers with parity generation/checking designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers. These parts include parity generator/checker to improve PC board density. TYPICAL PROPAGATION DELAY 6.5ns 6.5ns • Ideal in applications where high output drive and light bus loading • 74F655A combines 74F240 and 74F280A functions in one package are required (IIL is 40µA vs. FAST std of 600µA) TYPE 74F655A 74F656A TYPICAL SUPPLY CURRENT (TOTAL) 64mA 64mA • 74F656A combines 74F244 and 74F280A functions in one package • 74F655A Inverting • 74F656A Non-inverting • 3-State outputs sink 64mA and sou.

74F656A : The 74F655A and 74F656A are octal buffers and line drivers with parity generation/checking designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers. These parts include parity generator/checker to improve PC board density. TYPICAL PROPAGATION DELAY 6.5ns 6.5ns • Ideal in applications where high output drive and light bus loading • 74F655A combines 74F240 and 74F280A functions in one package are required (IIL is 40µA vs. FAST std of 600µA) TYPE 74F655A 74F656A TYPICAL SUPPLY CURRENT (TOTAL) 64mA 64mA • 74F656A combines 74F244 and 74F280A functions in one package • 74F655A Inverting • 74F656A Non-inverting • 3-State outputs sink 64mA and sou.

74F657 : The ’F657 contains eight non-inverting buffers with TRI-STATE outputs and an 8-bit parity generator checker It is intended for bus-oriented applications The buffers have a guaranteed current sinking capability of 24 mA (20 mA mil) at the A port and 64 mA (48 mA mil) at the B port Features Y 300 Mil 24-pin slimline DIP Y Combines ’F245 and ’F280A functions in one package Y TRI-STATE outputs Y B Outputs sink 64 mA (48 mA mil) Y 12 mA source current B side Y Input diodes for termination effects Commercial 74F657SPC 75F657SC (Note 1) Military 54F657SDM (Note 2) 54F657FM (Note 2) 54F657LM (Note 2) Package Number N24C J24F M24B W24C E28A Package Description 24-Lead (0 300 Wide) Molded Dual-In.

74F657 : The 74F657 is an octal transceiver featuring non–inverting buffers with 3–state outputs and an 8–bit parity generator/checker, and is intended for bus–oriented applications. The buffers have a guaranteed current sinking capability of 24mA at the A ports and 64mA at the B ports. The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active high) enables data from A ports to B ports; receive (active low) enables data from B ports to A ports. The output enable (OE) input disables both the A and B ports by placing them in a high impedance condition when the OE input is high. ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE D.

74F657 : The 74F657 contains eight non-inverting buffers with 3STATE outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A Port and 64 mA at the B Port. Features s 300 Mil 24-pin slimline DIP s Combines 74F245 and 74F280A functions in one package s 3-STATE outputs s B Outputs sink 64 mA s 12 mA source current, B side s Input diodes for termination effects Ordering Code: Order Number 75F657SC 74F657SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide.

74F657 : The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port. DW OR NT PACKAGE (TOP VIEW) T/R 1 A1 2 A2 3 A3 4 A4 5 A5 6 VCC 7 A6 8 A7 9 A8 10 ODD/EVEN 11 ERR 12 24 OE 23 B1 22 B2 21 B3 20 B4 19 GND 18 GND 17 B5 16 B6 15 B7 14 B8 13 PARITY The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port from the B port. When the .




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