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74F821

Part Number	74F821
Manufacturer	National
Description	10-Bit D-Type Flip-Flop
Published	May 28, 2005
Detailed Description	54F 74F821 10-Bit D-Type Flip-Flop December 1994 54F 74F821 10-Bit D-Type Flip-Flop General Description The ’F821 is a...
Datasheet	74F821 PDF File

Overview

54F 74F821 10-Bit D-Type Flip-Flop December 1994 54F 74F821 10-Bit D-Type Flip-Flop General Description The ’F821 is a 10-bit D-type flip-flop with TRI-STATE true outputs arranged in a broadside pinout The ’F821 is functionally and pin compatible with the AMD’s Am29821 Features Y Y TRI-STATE Outputs Direct replacement for AMD’s Am29821 Commercial 74F821SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 54F821SDM (Note 2) 74F821SC (Note 1) 54F821FM (Note 2) 54F821LM (Note 2) Note 1 Devices also available in 13 reel Use suffix e SCX J24F M24B W24C E28A Note 2 Military grade device with environmental and burn-in processing Use suffix e SDMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9595–1 IEEE IEC TL F 9595 – 3 TL F 9595 – 2 TL F 9595–5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9595 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 3 0 mA 24 mA (20 mA) D0 – D9 OE CP O0 – O9 Data Inputs Output Enable TRI-STATE Input Clock Input TRI-STATE Outputs Functional Description The ’F821 consists of ten D-type edge-triggered flip-flops This device has TRI-STATE true outputs for bus systems organized in a broadside pinning The buffered Clock (CP) and buffered Output Enable (OE) are common to all flipflops The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition With the OE LOW the content of the flip-flops are available at the outputs When the OE is HIGH the outputs go to the high impe...

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