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SP5848KGQP1S

Mitel Networks
Part Number SP5848KGQP1S
Manufacturer Mitel Networks
Description 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL
Published Jun 7, 2005
Detailed Description Preliminary Information SP5848 SP5848 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL Preliminary Information DS5076 Is...
Datasheet PDF File SP5848KGQP1S PDF File

SP5848KGQP1S
SP5848KGQP1S


Overview
Preliminary Information SP5848 SP5848 2.
2/1.
3GHz 3-Wire Bus Dual Low Phase Noise PLL Preliminary Information DS5076 Issue 1.
6 October 1999 Features G Ordering Information SP5848/KG/QP1S SP5848/KG/QP1T G G G Dual independent PLL frequency synthesisers in a single package, optimised for double conversion cable tuners, offering improved application 2.
2GHz up-synthesiser optimised for low phase noise up to comparison frequencies of 4MHz 1.
3GHz down-synthesiser optimised for low phase noise AND small step size Common reference oscillator and divider with independently selectable ratios for each synthesiser 10:1 programmable charge pump current ratio in up synthesiser 3-Wire bus programmable, each synthesiser indepently addressable Low power consumption, typ 100mW at 5V ESD protection, (Normal ESD handling procedures should be observed) Description The SP5848 is a dual PLL frequency synthesizer controlled by a 3-wire bus optimised for application in double conversion tuners.
Each synthesiser loop within the SP5848 is independently addressable and contains an RF programmable divider, phase/frequency detector and charge pump/loop amplifier section; a common reference frequency oscillator and divider chain is provided, whose ratios for each loop are independently programmable.
Both synthesisers are optimised for low phase noise performance and in addition synthesiser 2 is capable of operation with a low comparison frequency.
G G G G Applications G TV, VCR, and cable tuning systems PUMP 1 11 BIT COUNT RF1 INPUT 16/17 4 BIT COUNT DRIVE 1 15 BIT LATCH 2 BIT LATCH DATA CLOCK ENABLE DATA INTERFACE 5 BIT LATCH 29 DIVIDE 2 BIT LATCH PORT P0 PORT P1 16 BIT LATCH 1 BIT LATCH PUMP 2 12 BIT COUNT RF 2 INPUT 16/17 4 BIT COUNT DRIVE 2 Figure 1 Block Diagram 1 SP5848 Preliminary Information PORT P1 CHARGE PUMP 2 DRIVE 2 Vee 2 RF2 INPUT RF2 INPUT Vcc2 CRYSTAL CRYSTAL CAP Vee PORT P0 CHARGE PUMP 1 DRIVE 1 Vee 1 RF1 INPUT RF1 INPUT Vcc1 ENABLE DATA CLOCK QP20 Figure 2...



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