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MC14560B

Motorola
Part Number MC14560B
Manufacturer Motorola
Description NBCD Adder
Published Jul 22, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14559B See Page 398 MC14560B NBCD Adder The MC14560B adds two 4–bit numbers i...
Datasheet PDF File MC14560B PDF File

MC14560B
MC14560B

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14559B See Page 398 MC14560B NBCD Adder The MC14560B adds two 4–bit numbers in NBCD (natural binary coded decimal) format, resulting in sum and carry outputs in NBCD code.
This device can also subtract when one set of inputs is complemented with a 9’s Complementer (MC14561B).
All inputs and outputs are active high.
The carry input for the least significant digit is connected to VSS for no carry in.
L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout PD Tstg TL Parameter DC Supply Voltage Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package† Storage Temperature Lead Temperature (8–Second Soldering) Value Unit V V mA mW – 0.
5 to + 18.
0 – 0.
5 to VDD + 0.
5 ± 10 500 – 65 to + 150 260 • Diode Protection on All Inputs • Supply Voltage Range = 3.
0 Vdc to 18 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages.
_C _C 7 15 14 1 2 3 4 5 6 BLOCK DIAGRAM Cin A1 B1 A2 B2 A3 B3 A4 B4 S1 S2 S3 S4 Cout 13 12 11 10 9 * Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: Plastic “P and D/DW” Packages: – 7.
0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C TRUTH TABLE* Input A4 0 0 0 0 0 0 1 0 1 A3 0 0 1 1 1 1 0 1 0 A2 0 0 0 0 1 1 0 1 0 A1 0 0 0 0 1 1 0 0 1 B4 0 0 0 0 0 0 0 1 1 B3 0 0 0 0 1 1 1 0 0 B2 0 0 1 1 0 0 0 0 0 B1 0 0 1 1 0 0 1 0 1 Cin 0 1 0 1 0 1 0 0 1 Cout 0 0 0 0 1 1 1 1 1 S4 0 0 0 1 0 0 0 0 1 Output S3 0 0 1 0 0 0 0 1 0 S2 0 0 1 0 0 1 1 0 0 S1 0 1 1 0 1 0 1 0 1 VDD = PIN 16 VSS = PIN 8 * Partial truth table to show lo...


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