DatasheetsPDF.com

CY7C1373C

Part Number	CY7C1373C
Manufacturer	Cypress
Description	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
Published	Aug 19, 2005
Detailed Description	CY7C1371C CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (N...
Datasheet	CY7C1373C PDF File

Overview

CY7C1371C CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.
3V/2.
5V I/O power supply • Fast clock-to-output times — 6.
5 ns (for 133-MHz device) — 7.
5 ns (for 117-MHz device) — 8.
5 ns (for 100-MHz device) • Clock Enable (CEN) pin to enable clock and sus...

Similar Datasheet

CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM - Cypress Semiconductor
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture - Cypress
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture - Cypress
CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM - Cypress
CY7C1370DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM - Cypress Semiconductor
CY7C1370KV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM - Cypress Semiconductor
CY7C1370KV33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM - Cypress Semiconductor
CY7C1370KVE33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM - Cypress Semiconductor
CY7C1371B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM - Cypress Semiconductor
CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture - Cypress

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)