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CY7C1372D

Part Number	CY7C1372D
Manufacturer	Cypress
Description	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
Published	Aug 19, 2005
Detailed Description	CY7C1370D CY7C1372D 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512 K × 36/1 M × 18) ...
Datasheet	CY7C1372D PDF File

Overview

CY7C1370D CY7C1372D 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades are 250, 200, and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ 3.
3 V core power supply (VDD) ■ 3.
3 V/2.
5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 2.
6 ns (for 250 MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 65-ball FBGA package ■ IEEE 1149.
1 JTAG-compatible boundary scan ■ Burst capability – linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock op...

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